Cost-effective architecture of decoder circuits and futuristic scope in the era of nano-computing

Document Type : Article

Authors

1 Department of Electronics and Telecommunication, Veer Surendra Sai University of Technology, Burla, Sambalpur 768018, Odisha, India (Orchid Id: 0000-0003-2916-2903)

2 School of Electronics Engineering, Vellore Institute of Technology (VIT) - AP University, Amaravati, Andhra Pradesh, India (Orchid Id: 0000-0002-7907-0276)

Abstract

The goal of Very Large Scale Integration (VLSI) over the past several decades has been the miniaturisation of chip size, along with increased computing speed and decreased power consumption. Miniaturization of size, high computing speed, and low power consumption does not appear to be able to meet the demand of consumers at this time. Quantum dot cellular automata is a more promising methodology that has the potential to optimise power, speed, and area at the nano-computing scale. In the field of nanocomputing, combinational circuit design has seen a significant amount of research and development effort. This article presents a comprehensive review as well as a proposed design of a decoder that has an accurate clocking mechanism and the best design. In terms of cell count, total area, cell area, area coverage, latency, QCA cost, and quantum cost, the novel 2-to-4 decoder achieves values of 87, 0.10, 0.0281, 28.1, 2.5, 0.625, 0.25, which is better than the prior work. Comparing the 2-to-4 decoder design to a standard design, the improvement is 72.64 %, 80 %, 72.71 %, 28.1 %, 64.28 %, 97,44 and 92.85 % in cell count, total area, cell area, area coverage, latency, QCA cost, and Quantum cost, respectively.

Keywords

References

References:
1. Misra, N.K., Wairya, S., and Sen, B. "Design of conservative, reversible sequential logic for cost efficient emerging nano circuits with enhanced testability", Ain Shams Engineering Journal, 9(4), pp. 2027-2037 (2018).
2. Misra, N.K., Sen, B., and Wairya, S. "Novel conservative reversible error control circuits based on molecular QCA", Int. J. Comput. Appl. Technol., 56(1), pp. 1-17 (2017).
3. Rahmani, Y., Heikalabad, S.R., and Mosleh, M. "Design of a new multiplexer structure based on a new fault-tolerant majority gate in quantum-dot cellular automata", Optical and Quantum Electronics, 53(9), pp. 1-19 (2021).
4. Kaity, A. and Singh, S. "Optimized area efficient quantum dot cellular automata based reversible code converter circuits: Design and energy performance estimation", The Journal of Supercomputing, 77(10), pp. 11160-11186 (2021).
5. Afrooz, S. and Navimipour, N.J. "An effective nano design of demultiplexer architecture based on coplanar quantum-dot cellular automata", IET Circuits, Devices & Systems, 15(2), pp. 168-174 (2021).
6. Pathak, N., Misra, N.K., Bhoi, B.K., et al. "Optimization of parameters of adders and barrel shifter based on emerging QCA technology", Radioelectronics and Communications Systems, 64(10), pp. 535-547 (2021).
7. Sherizadeh, R. and Navimipour, N.J. "Designing a 2-to-4 decoder on nanoscale based on quantum-dot cellular automata for energy dissipation improving", Optik, 158, pp. 477-489 (2018).
8. Lantz, T. and Peskin, E. "A QCA implementation of a configurable logic block for an FPGA", IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006), pp. 1-10 (2006).
9. Kianpour, M. and Sabbaghi-Nadooshan, R. "A conventional design and simulation for CLB implementation of an FPGA quantum-dot cellular automata", Microprocessors and Microsystems, 38(8), pp. 1046- 1062 (2014).
10. Kianpour, M. and Sabbaghi-Nadooshan, R. "A novel modular decoder implementation in quantum-dot cellular automata (QCA)", In 2011 International Conference on Nanoscience, Technology and Societal Implications, pp. 1-5 (2011).
11. Goswami, M., Tanwar, R., Rawat, P., et al. "Configurable memory designs in quantum-dot cellular automata", International Journal of Information Technology, 13(4), pp. 1381-1393 (2021).
12. Banerjee, S., Bhattacharya, J., and Chatterjee, R., et al. "A novel design of 3 input 8 output decoder using quantum dot cellular automata", IEEE 7th Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON), pp. 1-6 (2016).
13. Vieira, L.G.L., Vieira, L.F.M., Vieira, M.A.M., et al. "Geometric greedy router in quantum-dot cellular automata", AEU-International Journal of Electronics and Communications, 128, 153498 (2021).
14. Navidi, A., Sabbaghi-Nadooshan, R., and Dousti, M. "TQCAsim: an accurate design and essential simulation tool for ternary logic quantum-dot cellular automata", Scientia Iranica, 29(6), pp. 3249-3256 (2021).
15. Kassa, S., Gupta, P., Kumar, M., et al. "Rotated majority gate-based 2n-bit full adder design in quantumdot cellular automata nanotechnology", Circuit World, 48(1), pp. 48-63 (2021).
16. Yaqoob, S., Ahmed, S., Naz, S.F., et al. "Design of efficient N-bit shift register using optimized D ip op in quantum dot cellular automata technology", IET Quantum Communication, 2(2), pp. 32-41 (2021).
17. Misra, N.K., Sen, B., Wairya, S., et al. "Testable novel parity-preserving reversible gate and low-cost quantum decoder design in 1D molecular-QCA", Journal of Circuits, Systems and Computers, 26(09), 1750145 (2017).
18. Pal, J., Pramanik, A.K., Sharma, J.S., et al. "An efficient, scalable, regular clocking scheme based on quantum dot cellular automata", Analog Integrated Circuits and Signal Processing, 107(3), pp. 659-670 (2021).
Scientia Iranica
Volume 30, Issue 2
Transactions on Computer Science & Engineering and Electrical Engineering (D)
March and April 2023
Pages 477-491

Files

History

  • Receive Date: 01 August 2021
  • Revise Date: 28 May 2022
  • Accept Date: 19 September 2022

Share

How to cite

Statistics