Cost-effective architecture of decoder circuits and futuristic scope in the era of nano-computing

Document Type : Article

Authors

1 Department of Electronics and Telecommunication, Veer Surendra Sai University of Technology, Burla, Sambalpur 768018, Odisha, India (Orchid Id: 0000-0003-2916-2903)

2 School of Electronics Engineering, Vellore Institute of Technology (VIT) - AP University, Amaravati, Andhra Pradesh, India (Orchid Id: 0000-0002-7907-0276)

Abstract

The goal of Very Large Scale Integration (VLSI) over the past several decades has been the miniaturisation of chip size, along with increased computing speed and decreased power consumption. Miniaturization of size, high computing speed, and low power consumption does not appear to be able to meet the demand of consumers at this time. Quantum dot cellular automata is a more promising methodology that has the potential to optimise power, speed, and area at the nano-computing scale. In the field of nanocomputing, combinational circuit design has seen a significant amount of research and development effort. This article presents a comprehensive review as well as a proposed design of a decoder that has an accurate clocking mechanism and the best design. In terms of cell count, total area, cell area, area coverage, latency, QCA cost, and quantum cost, the novel 2-to-4 decoder achieves values of 87, 0.10, 0.0281, 28.1, 2.5, 0.625, 0.25, which is better than the prior work. Comparing the 2-to-4 decoder design to a standard design, the improvement is 72.64 %, 80 %, 72.71 %, 28.1 %, 64.28 %, 97,44 and 92.85 % in cell count, total area, cell area, area coverage, latency, QCA cost, and Quantum cost, respectively.

Keywords

References

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Scientia Iranica
Volume 30, Issue 2
Transactions on Computer Science & Engineering and Electrical Engineering (D)
March and April 2023
Pages 477-491

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