1
EE Department, Sharif University of Technology, Tehran, P.O. Box: 11155-9363, Iran
2
EE Department, Sharif University of Technology, Tehran, P.O. Box: 11155-9363, Iran.
Abstract
A new approach for the design of two-stage Miller-compensated CMOS op amps is presented. The paper studies the basic relations between power consumption, unity-gain bandwidth, biasing region, technology parameters, and the external capacitive load. As a result, simple and ecient design guides are provided to achieve the minimum possible power consumption for the given speci cations and for short-channel devices. It is shown that the conventional design proce- dures do not always result in minimum power op amps. The presented results are also veri ed by Spectre simulations.
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