A Simple and Practical PLL for Single-Phase Grid-Tied Inverters Facing with Abnormal Grid Voltage Conditions

Document Type : Article

Authors

1 Department of Electrical Engineering, K. N. Toosi University of Technology, Tehran, Iran

2 Department of Electrical Engineering, Isfahan University, Isfahan, Iran

10.24200/sci.2024.64445.8946

Abstract

As the number of distributed generation (DG)
systems connected to the utility grid is increasing the issue
of synchronization between the DGs and the grid is
becoming more profound. This paper presents a simple
phase-locked loop (PLL) for the proper operation of the
inverters even when the utility grid voltage is subjected to
considerable abnormal conditions, such as changes in
frequency and voltage amplitude or the presence of grid
voltage harmonics. The proposed PLL is based on zero crossing points, which makes it robust and compatible in
various grid voltage frequencies and amplitudes. Since in
the proposed PLL the grid voltage phase and amplitude are
extracted without Park matrix and notch filter, it demands
lower number of clocks for the calculations with respect to the
existing methods. This feature is practically desired since
the proposed PLL can be executed on a simple and low-cost
microcontroller. The performance of the proposed PLL has
been evaluated by simulation and experimental tests. The
results demonstrate the functionality of the proposed PLL
on a 1.6 kW single-phase inverter.

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Main Subjects



Articles in Press, Accepted Manuscript
Available Online from 23 December 2024
  • Receive Date: 08 May 2024
  • Revise Date: 06 October 2024
  • Accept Date: 23 December 2024