Department of Computer Engineering and IT,National Institute of Pharmaceutical Education and Research
Abstract
In this study, we propose a multicast switching system called the Blocking Reduction
Multiple Slot Cell Scheduler (BRMSCS) switch. The BRMSCS switch consists of shared memory banks, a
crossbar fabric and the BRMSCS scheduler. Our goals are to relieve the blocking situation in the scheduler
and to guarantee freedom from a memory access con
ict, that is, no more than two output ports should
access di erent cells that come from the same input port. To meet the goals, the BRMSCS scheduler can
quickly insert address cells into a scheduling table and ll the scheduling table as full as possible. The
simulation results show that the BRMSCS scheduler can eciently insert the address cells into the con
ict
free locations of the scheduling table and has the advantage of reducing blocking.
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