Clock Boosting Router: Increasing the Performance of an Adaptive Router in Network-on-Chip (NoC)


Department of Electrical Engineering,University of California


In this paper, a simple and ecient clock boosting mechanism to increase the performance of an
adaptive router in Network-on-Chip (NoC) is proposed. One of the most serious disadvantages
of a fully adaptive wormhole router is performance degradation due to the routing decision time.
The key idea to overcome this shortcoming is the use of di erent clocks in a head
it and
its. The simulation results show that the proposed clock boosting mechanism enhances
the performance of the original adaptive router by increasing the accepted load and decreasing
the average latency in the region of e ective bandwidth. The enhanced throughput of a router
results in power saving by reducing the operating frequency of a router for certain communication
bandwidth requirements.