A 0.18 m single chip GPS receiver, with 19.5 mA current consumption, is implemented in
6.5 mm2. Low-IF architecture was used for a high level of integration and low power consumption.
A serial input digital control, with additional testing structure, not adding more than 4% to the
Si area, is used in the actual RF circuits, in case of problems, minimizing the number of Si runs.
Jenabi, M., Fotowat Ahmady, A., & Riahi, N. (2008). A Programmable GPS Receiver with Test Circuits in 0.18 m CMOS. (e2967). Scientia Iranica, 15(2), e2967
MLA
Jenabi, M., Fotowat Ahmady, A., & Riahi, N. "A Programmable GPS Receiver with Test Circuits in 0.18 m CMOS" .e2967 , Scientia Iranica, 15, 2, 2008, e2967.
HARVARD
Jenabi M., Fotowat Ahmady A., Riahi N. (2008). 'A Programmable GPS Receiver with Test Circuits in 0.18 m CMOS', Scientia Iranica, 15(2), e2967.
CHICAGO
M. Jenabi, A. Fotowat Ahmady & N. Riahi, "A Programmable GPS Receiver with Test Circuits in 0.18 m CMOS," Scientia Iranica, 15 2 (2008): e2967,
VANCOUVER
Jenabi M., Fotowat Ahmady A., Riahi N. A Programmable GPS Receiver with Test Circuits in 0.18 m CMOS. Scientia Iranica. 2008;15(2):e2967.
