A Programmable GPS Receiver with Test Circuits in 0.18 m CMOS


1 Department of Engineering,Auburn University

2 Department of Engineering,Alzahra University


A 0.18 m single chip GPS receiver, with 19.5 mA current consumption, is implemented in
6.5 mm2. Low-IF architecture was used for a high level of integration and low power consumption.
A serial input digital control, with additional testing structure, not adding more than 4% to the
Si area, is used in the actual RF circuits, in case of problems, minimizing the number of Si runs.