Department of Mathematical Sciences,Sharif University of Technology
Abstract
The architecture of a hardwired simulator for implementation of a iscrete event-driven simulation of digital systems at the logic level is resented. In the design of this system, attempts have been made to utilize echniques of high performance computing to have a system capable of simulating he digital circuits rapidly. The centralized event-driven simulation algorithm hosen here, has the advantages of being efficient and conceptually traightforward. The high reliability of the simulator has been taken care of hrough a collection of handshake signals between each two of the three main odules.
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