A 4-X Gain 9-Level Multilevel Inverter Topology with Reduced Part Count

Jena, Kasinath; Gupta, Krishna Kumar; Kumar, Dhananjay

doi:10.24200/sci.2025.65182.9341

A 4-X Gain 9-Level Multilevel Inverter Topology with Reduced Part Count

Articles in Press

Document Type : Research Article

Authors

¹ Department of Electrical and Electronics Engineering, ARKA JAIN University, Jharkhand, India

² Department of Electrical & Instrumentation Engineering, Thapar Institute of Engineering & Technology Patiala, India

³ Department of Electrical Engineering, Government Engineering College, Siwan, India

10.24200/sci.2025.65182.9341

Abstract

This research presents a novel quadruple boost 9-level single-phase switched-capacitor (SC) inverter. The proposed topology (PT) comprises eight semiconductor switches, two capacitors, one power diode, and a single supply source unit that can synthesize 9 levels of voltage at the output terminal. A brief description of structural design, operating principle, modulation strategy, and determination of optimum values of the capacitances are presented in this work. Simulation and experimental studies have been carried out under different loading conditions to validate the effectiveness of the PT. Further, a fair comparative study with state-of-the-art SC topologies regarding component count per level, gain, total standing voltage, and cost function proves the merits of the suggested novel work.

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