Comprehensive stochastic analysis method for tree-type PDNs and ground pollution on mixed-signal PCBs

Document Type : Article

Author

Department of Electrical Engineering, Faculty of Engineering, Alzahra University, Tehran, Iran

Abstract

In this paper, a stochastic analysis method is proposed for extraction and evaluation of power distribution map (PDM) in system printed circuit board (PCB). This is conducted based on some system-level information including placement and routing geometry, power distribution network (PDN), component package parasitic, and voltage regulator module (VRM). A simple model for supply current of two constituent blocks of electronic systems is analytically extracted. The worst-case simultaneous operation of all consumers are considered for PDM extraction. The approach is applied to a specific designed and fabricated mixed signal board. PDM is beneficial in the placement process of decoupling capacitance or noisy components in an optimum and right location. Also, the proposed approach can be considered as a verification step of PCB design flow and be applicable before routing merely based on the placement data of the system components. This enables the designer to predict the upcoming problems in layout and hastens the process of design verification.

Keywords

Main Subjects

References

References:
1. Song, J., Jung, D.H., Shin, J., et al. "Novel target-impedance extraction method-based optimal PDN design for high-performance SSD using deep reinforcement learning", IEEE Trans. Signal and Power Integrity, 2, pp. 1-12 (2023). DOI: 10.1109/TSIPI.2023.3235310.
2. Zhang, L., Juang, J., Kiguradze, Z., et al. "Efficient DC and AC impedance calculation for arbitrary-shape and multilayer PDN using boundary integration", IEEE Trans. Signal and Power Integrity, 1, pp. 1-11 (2022). DOI: 10.1109/TSIPI.2022.3164037.
3. Wada, S., Hayashi, Y., Fujimoto, D., et al. "Measurement and analysis of electromagnetic information leakage from printed circuit board power delivery network of cryptographic devices", IEEE Trans. Electromagn. Compat., 63(5), pp. 1322-1332 (2021). DOI: 10.1109/TEMC.2021.3062417.
4. Suenaga, H., Tsukioka, A., Jike, K., et al. "Compact simulation of chip-to-chip active noise coupling on a system PCB board", IEEE Letters Electromagn. Compat. Practice and Applications, 2(1), pp. 15-20 (2020). DOI: 10.1109/LEMCPA.2020.2983687.
5. Zhou, P., Pei, X., Chen, Q., et al. "EMI behavioral model based CM noise prediction method for DC power system considering multi-noise coupling", IEEE Trans. on Power Electronics, 38(4), pp. 4658-4667 (2023). DOI: 10.1109/TPEL.2023.3236017.
6. Li, N. and Miao, M. "Design of EMI and suppression structure based on bar-via", Microelectronics Journal, 112, pp. 1-9 (2021). DOI: 10.1016/j.mejo.2021.105049.
7. Yousaf, J., Nah, W., Majali, E.R.A., et al. "Rapid characterization of efficient system level ESD protection strategy using coupling transfer function", Micro Electronics Journal, 110, pp. 1-13 (2021). DOI: 10.1016/j.mejo.2021.105004.
8. Zhu, Z., Zhao, Y., Yan, W., et al. "Modeling of line impedance stabilization network impedance characteristic based on genetic algorithm", Microelectronics Journal, 113, pp. 1-8 (2021). DOI: 10.1016/j.mejo.2021.105095.
9. Kerrouche, B., Bensetti, M., and Zaoui, A. "EMI modeling considering the impedance behavior of isolated off-line converter", Microelectronics Reliability, 105, pp. 1-9 (2020). DOI: 10.1016/j.microrel.2019.113562.
10. Benfca, J., Vargas, F., Soares, M.F., et al. "Conducted EMI susceptibility analysis of a COTS processor as function of aging", Microelectronics Reliability, 114, pp. 1-7 (2020). DOI: 10.1016/j.microrel.2020.113884.
11. Kraiem, S., Hamouda, M., and Slama, J.B.H. "Conducted EMI mitigation in transformer-less PV inverters based on intrinsic MOSFET parameters", Microelectronics Reliability, 114, pp. 8-14 (2020). DOI: 10.1016/j.microrel.2020.113876.
12. Sun, J., Wang, H., Wu, K., et al. "A patternbased analytical method for impedance calculation of the power distribution network in mobile platforms", IEEE Trans. Electromagn. Compat., 63(3), pp. 912- 921 (2021). DOI: 10.1109/TEMC.2020.3026048.
13. Yang, S., Cao, Y.S., Ma, H., et al. "PCB PDN pre-layout library for top-Layer inductance and the equivalent model for decoupling capacitors", IEEE Trans. Electromagn. Compat., 60(6), pp. 1898-1906 (2018). DOI: 10.1109/TEMC.2017.2768226.
14. Cao, Y.S., Makharashvili, T., Cho, J., et al. "Inductance extraction for PCB pre-layout power integrity using PMSR method", IEEE Trans. Electromagn. Compat., 59(4), pp. 1339-1346 (2017). DOI:10.1109/TEMC.2017.2672726.
15. Paulis, F.D., Zhang, T., and Fan, J. "Signal/Power integrity analysis for multilayer printed circuit boards using cascaded S-parameters", IEEE Trans. Electromagn. Compat., 52(4), pp. 1008-1018 (2010). DOI: 10.1109/TEMC.2010.2072784.
16. Archambeault, B., Brench, C., and Connor, S. "Review of printed-circuit-board level EMI-EMC issues and tools", IEEE Trans. Electromagn. Compat., 52(2), pp. 455-461 (2010). DOI: 10.1109/TEMC.2010.2044182.
17. Mehri, M. and Masoumi, N. "Statistical prediction and quantification of radiated susceptibility for electronic systems PCB in electromagnetic polluted environments", IEEE Trans. Electromagn. Compat., 59(2), pp. 498-508 (2017). DOI: 10.1109/TEMC.2016.2610463.
18. Hoyos, S., Garcia, J.A., and Arce, G.R. "Mixedsignal equalization architectures for printed circuit board channels", IEEE Trans. on Circuits and Syst. I: Reg. Papers, 51(2), pp. 264-274 (2004). DOI: 10.1109/ICASSP.2002.5745476.
19. Rabaey, J.M., Chandrakasan, A., and Nikolic, B., In Digital Integrated Circuits, A Design Perspective, 2nd Edn., Pearson Education (2003).
20. Mehri, M., Kouhani, M.H.M., Masoumi, N., et al. "New approach to VLSI buffer modeling, consideringovershooting effect", IEEE Trans. Very Large Scale Integr. Syst., 21(8), pp. 1568-1572 (2013). DOI: 10.1109/TVLSI.2012.2211629.
21. Bisdounis, L. and Koufopavlou, O. "Short-circuit energy dissipation modeling for sub-micrometer CMOS gates", IEEE Trans. on Circuits and Syst.-Part I: Fundamental Theory and Applications, 47(9), pp. 1350- 1361 (2000). DOI: 10.1109/81.883330.
22. Rossello, J.L. and Segura, J. "Charge-based analytical model for the evaluation of power consumption in submicron CMOS buffers", IEEE Trans. Computer- Aided Design of Integr. Circuits and Syst., 21(4), pp. 433-448 (2002). DOI: 10.1109/43.992767.
23. Bowman, K.A., Austin, B.L., Eble, J.C., et al. "A physical alpha power law MOSFET model", IEEE Journal of Solid-State Circuits, 34(10), pp. 1410-1414 (1999). DOI: 10.1109/4.792617.
24. Turgis, S. and Auvergne, D. "A novel macro-model for power estimation in CMOS structures", IEEE Trans. Computer-Aided Design of Integr. Circuits and Syst., 17(11), pp. 1090-1098 (1998). DOI: 10.1109/43.736183.
25. Wang, J., Lu, J., Chu, X., et al. "Modeling and simulation of planes with decoupling capacitors", IEEE Trans. on Components, Packaging and Manufacturing Technology, 6(7), pp. 1087-1098 (2016). DOI: 10.1109/TCPMT.2016.2573842.
26. Park, H., Park, J., Kim, S., et al. "Deep reinforcement learning-based optimal decoupling capacitor design method for silicon interposer-based 2.5-D/3-D ICs", IEEE Trans. on Components, Packaging and Manufacturing Technology, 9(9), pp. 1835-1846 (2019). DOI: 10.1109/TCPMT.2020.2972019.
27. Tripathi, J.N., Sharma, V.K., and Shrimali, H. "A review on power supply induced jitter", IEEE Trans. on Components, Packaging and Manufacturing Technology, 9(9), pp. 511-524 (2019). DOI: 10.1109/TCPMT.2018.2872608.
28. Zhang, M., Li, Y., and Li, L. "Analyze and design high-speed power delivery networks using new multiinput impedances in printed circuit boards", IEEE Trans. Microw. Theory and Techn., 57(7), pp. 1818- 1831 (2009). DOI: 10.1109/TMTT.2009.2022821.
29. Zhang, M. and Mao, J. "A new systematic method for the modeling, analysis, and design of high-speed power-delivery networks by using distributed port", IEEE Trans. Microw. Theory and Techn., 58(11), pp. 2940-2951 (2010). DOI: 10.1109/TMTT.2010.2079090.
30. Mehri, M. "Stochastic estimation of total radiated power from PCB signal/PDN layout using EMI radiation resistance", Microelectronics Journal, 116, pp. 1-10 (2021). DOI: 10.1016/j.mejo.2021.105256.
31. Mehri, M. "A circuit level analysis of power distribution network on a PCB layout exposed to intentional/unintentional electromagnetic threats", Integration, 89, pp. 25-36 (2023). DOI: 10.1016/j.vlsi.2022.11.008.
32. Heidari, S., Mehri, M., and Masoumi, N. "Statistical prediction of planar power consumption distribution in digital system layout/PCB", The 21th IEEE Workshop on Signal and Power Integrity, (SPI2017), Italy, May (2017). DOI: 10.1109/SaPIW.2017.7944042.
33. Carlson, A.B., Crilly, P.B., and Rutledge, J.C., In Communication Systems: An Introduction to Signals in Electrical Communication, 4th Edn., McGraw-Hill (2002). 
34. Chen, G. and Friedman, E.G. "An RLC interconnect model based on Fourier analysis", IEEE Trans. on Computer-Aided Design of Integr. Circuits and Syst., 24(2), pp. 170-183 (2005). DOI: 10.1109/TCAD.2004.841065.
35. Rashid, M.H., In Power Electronics: Circuits, Devices and Applications, 4th Edn., Pearson (2013). 
Scientia Iranica
Volume 31, Issue 17
Transactions on Computer Science & Engineering and Electrical Engineering (D)
November and December 2024
Pages 1463-1478

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History

  • Receive Date: 08 March 2021
  • Revise Date: 13 March 2023
  • Accept Date: 25 June 2023

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