FoM Optimization in Class-C Oscillators

Document Type : Research Note

Authors

1 Department of Electrical Engineering, Sharif University of Technology, Tehran, Iran

2 Department of Electrical Engineering, Cornell University, Ithaca, New York, USA

Abstract

In this paper, a new approach to optimize phase noise and figure of merit (FoM) in class-C oscillators is presented. This approach recruits DC voltage of the common source node of the switching
pair transistors as an indicator to achieve the best performance of a class-C oscillator. The proposed indicator has the advantages of not introducing any loading effect to the output node, and ndependency from PVT changes. The method is simple and applicable to any oscillator with class-C topology, and with some modifications it would be applied to other oscillator topologies like class-B. The idea is verified using theoretical analysis, and circuit simulations on 0.18um CMOS technology at 2GHz oscillation frequency. Moreover, a discrete prototype is fabricated at 15MHz and measurement results are provided which further validate feasibility of this approach.

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Articles in Press, Accepted Manuscript
Available Online from 18 June 2023
  • Receive Date: 19 January 2021
  • Revise Date: 24 September 2022
  • Accept Date: 18 June 2023