References:
1. Safoev, N. and J.-C. Jeon. "Design of highperformance QCA incrementer/decrementer circuit based on adder/subtractor methodology”, Microprocessors and Microsystems, 72, 102927 (2020). https://doi.org/10.1016/j.micpro.2019.102927.
2. Sharifi, F., Moaiyeri, M.H., Navi, K., et al. "Ultralow- power carbon nanotube FET-based quaternary logic gates”, International Journal of Electronics, 103(9), pp. 1524-1537 (2016). https://doi.org/10.1080/21681724.2016.1138506.
3. Nayeri, M. and Keshavarzian, P. "A novel design of quaternary inverter gate based on GNRFET”, International Journal of Nanoscience and Nanotechnology, 15(3), pp. 211-217 (2019). https://www.ijnnonline.net/article_36253_5469f735c 62b94520f48dbc0399b6b34.pdf.
4. Akbari-Hasanjani, R., Sabbaghi-Nadooshan, R., and Tanhayi, M.R. "New polarization and power calculations with error elimination in ternary QCA”, Computers and Electrical Engineering, 96, p. 107557 (2021). https://doi.org/10.1016/j.compeleceng.2021.107557.
5. Mohammadi Mohaghegh, S., Sabbaghi-Nadooshan R., and Mohammadi, M. "Design of a ternary QCA multiplier and multiplexer: a model-based approach”, Analog Integrated Circuits and Signal Processing, 101, pp. 23-29 (2019). https://doi.org/10.1007/s10470-019-01465-3.
6. Lent, C.S., Tougaw, P.D., Porod, W., et al. "Quantum cellular automata”, Nanotechnology, 4(1), p. 49 (1993). https://doi.org/10.1088/0957-4484/4/1/004.
7. Shalamzari, Z.D., Zarandi, A.D., and Reshadinezhad, M.R. "Newly multiplexer-based quaternary half-adder and multiplier using CNTFETs”, AEU-International Journal of Electronics and Communications, 117, p. 153128 (2020). https://doi.org/10.1016/j.aeue.2020.153128.
8. Akbari-Hasanjani, R. and Sabbaghi-Nadooshan, R."Design and simulation of innovative QCA quaternary logic gates”, Advanced Theory and Simulations, 4(9), 2100069 (2021). https://doi.org/10.1002/adts.202100069.
9. Akbari-Hasanjani, R. and Sabbaghi-Nadooshan, R. "New design of binary to ternary converter”, IETE Journal of Research, 69(4), pp. 2212-2223 (2023). https://doi.org/10.1080/03772063.2021.1886881.
10. Haghparast, M. and Dousttalab, N. "Design of new reversible quaternary flip-flops”, International Journal of Quantum Information, 15(04), p. 1750024 (2017). https://doi.org/10.1142/S0219749917500241.
11. Ahmadpour, S.-S. and Mosleh, M. "New designs of fault-tolerant adders in quantum-dot cellular automata”, Nano Communication Networks, 19, pp. 10-25 (2019). https://doi.org/10.1016/j.nancom.2018.11.001.
12. Orlov, A.O., Amlani, I., Bernstein, G., et al. "Realization of a functional cell for quantum-dot cellular automata”, Science, 277(5328), pp. 928-930 (1997). https://doi.org/10.1126/science.277.5328.928.
13. Arjmand, M.M., Soryani, M., and Navi, K. "Coplanar wire crossing in quantum cellular automata using a ternary cell”, IET Circuits, Devices and Systems, 7(5), pp. 263-272 (2013). https://doi.org/10.1049/iet-cds.2012.0366.
14. Babaie, S., Sadoghifar, A., and Bahar, A.N. "Design of an efficient multilayer arithmetic logic unit in quantum-dot cellular automata (QCA)”, IEEE Transactions on Circuits and Systems II: Express Briefs 66(6), pp. 963-967 (2018). https://doi.org/10.1109/TCSII.2018.2873797.
15. Sasamal, T.N., Singh, A.K. and Mohan, A. "An efficient design of quantum-dot cellular automata based 5-input majority gate with power analysis”, Microprocessors and Microsystems, 59, pp. 103-117 (2018). https://doi.org/10.1016/j.micpro.2018.03.002.
16. Bajec, I.L., Zimic, N., and Mraz, M. "The ternary quantum-dot cell and ternary logic”, Nanotechnology, 17(8), p. 1937 (2006). https://doi.org/10.1088/0957-4484/17/8/023.
17. Pecar, P., Janez, M., Zimic, N., et al. “The ternary quantum-dot cellular automata memorizing cell”, In 2009 IEEE Computer Society Annual Symposium on VLSI, pp. 223-228 (IEEE, 2009). https://doi.org/10.1109/ISVLSI.2009.32.
18. Rahmani, Y., Heikalabad, S.R., and Mosleh, M. "Design of a new multiplexer structure based on a new fault-tolerant majority gate in quantum-dot cellular automata”, Optical and Quantum Electronics, 53, pp. 1-19 (2021). https://doi.org/10.1007/s11082-021-03179-1.
19. Safaiezadeh, B., Mahdipour, E., Haghparast, M., et al. "Design and simulation of efficient combinational circuits based on a new XOR structure in QCA technology”, Optical and Quantum Electronics, 53, pp. 1-16 (2021). https://doi.org/10.1007/s11082-021-03294-z.
20. Seyedi, S., Otsuki, A., and Navimipour, N.J. "A new cost-efficient design of a reversible gate based on a nano-scale quantum-dot cellular automata technology”, Electronics, 10(15), 1806 (2021). https://doi.org/10.3390/electronics10151806.
21. Sheibani, H. and Rahimi, E. "Single-electron fault tolerance in quantum cellular automata majority gate”, Journal of Circuits, Systems and Computers, 30(09), 2150168 (2021). https://doi.org/10.1142/S0218126621501681.
22. Zahmatkesh, M., Tabrizchi, S., Mohammadyan, S., et al. "Robust coplanar full adder based on novel inverter in quantum cellular automata”, International Journal of Theoretical Physics, 58, pp. 639-655 (2019). https://doi.org/10.1007/s10773-018-3961-6.
23. Ardesi, Y., Pulimeno, A., Graziano, M., et al. "Effectiveness of molecules for quantum cellular automata as computing devices”, Journal of Low Power Electronics and Applications, 8(3), p. 24 (2018). https://doi.org/10.3390/jlpea8030024.
24. Safaiezadeh, B., Mahdipour, E., Haghparast, M., et al. "Novel design and simulation of reversible ALU in quantum dot cellular automata”, The Journal of Supercomputing, 78(1), pp. 868-882 (2022). https://doi.org/10.1007/s11227-021-03933-y.
25. Peng, F., Zhang, Y., Kuang, R., et al. "Spars: A full flow quantum-dot cellular automata circuit design tool”, IEEE Transactions on Circuits and Systems II: Express Briefs, 68(4), pp. 1233-1237 (2020). https://doi.org/10.1109/TCSII.2020.3039532.
26. Macucci, M., Gattobigio, M., Bonci, L., et al. "A QCA cell in silicon-on-insulator technology: theory and experiment”, Superlattices and Microstructures, 34(3- 6), pp. 205-211 (2003). https://doi.org/10.1016/j.spmi.2004.03.010.
27. Hofmann, M., Weidenfeller, L., Supreeti, S., et al. "Mix-and-match lithography and cryogenic etching for NIL template fabrication”, Microelectronic Engineering, 224, p. 111234 (2020). https://doi.org/10.1016/j.mee.2020.111234.
28. Gao, P., Pu, M., Ma, X., et al. "Plasmonic lithography for the fabrication of surface nanostructures with a feature size down to 9 nm”, Nanoscale, 12(4), pp. 2415-2421 (2020). https://doi.org/10.1039/C9NR08153D.
29. Chen, W. and Ahmed, H. "Fabrication of 5–7 nm wide etched lines in silicon using 100 keV electron-beam lithography and polymethylmethacrylate resist”, Applied physics letters, 62(13), p. 1499-1501(1993). https://doi.org/10.1063/1.109609.
30. Päivänranta, B., Langner, A., Kirk, E., et al. "Sub-10 nm patterning using EUV interference lithography”, Nanotechnology, 22(37), p. 375302 (2011). https://doi.org/10.1088/0957-4484/22/37/375302.
31. Akbari-Hasanjani, R. and Sabbaghi-Nadooshan, R. "Innovation Quinary and n-Value toward Fuzzy Logic QCA Cell Design”, Advanced Theory and Simulations, 5(2), p. 2100304 (2022). https://doi.org/10.1002/adts.202100304.