An efficient hardware implementation for a motor imagery brain computer interface system

Document Type : Article

Authors

Department of Electrical Engineering, Sharif University of Technology, Tehran, Iran

Abstract

Brain Computer Interface (BCI) systems, which are based on motor imagery, enable human to command artificial peripherals by merely thinking to the task. There is a tremendous interest in implementing BCIs on portable platforms, such as Field Programmable Gate Arrays (FPGAs) due to their low-cost, low-power and portability characteristics. This article presents the design and implementation of a Brain Computer Interface (BCI) system based on motor imagery on a Virtex-6 FPGA. In order to design an accurate algorithm, the proposed method avails statistical learning methods such as Mutual Information (MI), Linear Discriminant Analysis (LDA) and Support Vector Machine (SVM). It also uses Separable Common Spatio Spectral Pattern (SCSSP) method in order to extract features. Simulation results prove achieved performances of 73.54% for BCI Competition III-dataset V, 67.2% for BCI Competition IV-dataset 2a with all four classes, 80.55% for BCI Competition IV-dataset 2a with the first two classes, and 81.9% for captured signals. Moreover, the final reported hardware resources determine its efficiency as a result of using retiming and folding techniques from the VLSI architecture perspective. The complete proposed BCI system not only achieves excellent recognition accuracy but also remarkable implementation efficiency in terms of portability, power, time, and cost.

Keywords

References

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History

  • Receive Date: 09 August 2017
  • Revise Date: 30 March 2018
  • Accept Date: 04 August 2018

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