Department of Electrical Engineering, Indian Institute of Technology (IIT)-Bombay, Mumbai, MH, India
The design challenges of voltage reference generators in CMOS technology have increased over the years in low voltage low power CMOS integrated circuits constituting analog, digital and mixed-signal modules. The emergence of hand-held power autonomous devices push the power consumption limit to nW regime. Along with these confrontations, limited full scale range of data converters at low supply levels demands accurate reference voltage generators. This paper reviews the allied design challenges and discusses the evolved methodologies to tackle them. This paper also prominently retrospect the sub -1V voltage reference topologies presented in the literature along with classic bandgap based voltage reference topologies. Non- bandgap (only CMOS) based reference architectures are proven to be area and power efficient but always have to be accompanied with auxiliary on/off chip trimming mechanism for high accuracy. We also provide insightful analysis of the voltage reference topologies, required by the designers.