Department of Electronics and Communication Engg.,National Institute of Technology, Durgapur, West Bengal, India
Department of Electrical Engg.,National Institute of Technology, Durgapur, West Bengal, India
This paper presents the analysis of static noise margin (SNM), power dissipation, access time and dynamic noise margin of a novel low power proposed 8T static random access memory (SRAM) cell for read operation. In the proposed structure two voltage sources are used, one is connected with the Bit line and the other is connected with Bitbar line in order to reduce the voltage swing at the output nodes of the bit and the bit bar lines. Simulation results for read static noise margin, read power dissipation, read access time and dynamic noise margin have been compared to those of other SRAM cells, reported in different literatures. It is shown that the proposed SRAM cell has better static noise margin and dissipates lesser power in comparison to other SRAM cells. Analog and schematic simulations have been done in 45nm environment with the help of Microwind 3.1 by using BSimM4 model.