Retracted: Thermally-aware circuit modeling and performance analysis of single-walled carbon nanotube bundle as VLSI interconnects

Document Type: Article

Abstract

Temperature-dependent delay, power dissipation, and Power Delay Product (PDP) are analyzed in a single-walled carbon nanotube (SWCNT) bundle interconnect. Thermally-aware circuit model for a metallic SWCNT bundle is presented. The results are compared with those of the currently used copper interconnects at 22 nm technology node. It is seen that delay, power dissipation, and PDP of SWCNT bundle interconnect increase with a rise in temperature from 300 K to 450 K at di erent interconnect lengths from 100 m to 1000 m. It is also observed that with rise in temperature, SWCNT bundle has a lower delay than that of copper for all interconnect lengths, whereas the reverse is true for power dissipation. In addition, with rise in temperature from 300 K to 450 K, for interconnect lengths at 100 m and 400 m, SWCNT bundle has lower PDP compared to copper interconnects, whereas the reverse is true for interconnect lengths at 700 m and 1000 m. Moreover, relative average improvement in delay, power, and PDP using thermally-aware resistance model is estimated in comparison with temperatureindependent resistance model of an SWCNT bundle. Based on simulation results, the thermally-aware resistance model of a SWCNT bundle achieved improvement in accuracy
of delay, power, and PDP estimation of about 22.44%, 7.59%, and 31.96%, respectively, on average.

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