A low power 10-bit ash analog-to-digital converter with divide and collate subranging conversion scheme

Document Type : Research Note

Authors

1 Department of Electronics and Communication Engineering, National Institute of Technology Meghalaya, Shillong 793003, IN

2 Department of Electronics and Communication Engineering, Indian Institute of Information Technology Pune, Saswad-Bopdev Rd, Pune 411048, IN

Abstract

The sampling rate plays a key role in wireless applications at very high-frequency range. Flash analog-to-digital converter (ADC) betters the slow converter counterparts in this regard but bulky at inevitable high resolutions. A state-of-the-art Divide and Collate (DnC) algorithm is proposed to design the flash ADC at subranging levels. The offset voltage is kept at a minimum through the comparators used for coarse and fine conversion separately. The kick-back noise is also reduced by using sample and hold switches at the input. The 10-bit ADC architecture is designed with 45-nm CMOS technology and analyzed in the SPECTRE environment. A trivial variation in the transconductance with temperature is observed and consequently the offset drift with temperature is found to be 0.015 mV/'C. The design improves the INL by 0.42 LSB and DNL by 0.3 LSB. Signal-to-noise-and-distortion (SNDR) ratio and spurious-free dynamic range (SFDR) are 51.8 dB and 62 dB respectively at a frequency range near the Nyquist rate with a supply voltage of 1 V and input frequency of 500 MHz. Subranging scheme minimizes the comparator requirements which is reflected in the 44% reduction in the power dissipation.

Keywords

Main Subjects


References
1. Kuo, K.C. A 1.2 V 10 bits 100 MS/s analog-to-digital
converter with a 8-stage pipeline and a 2 bits 
ash
ADC", In Proceedings of the International Conference
on Applied System Innovation, pp. 1638{1641, IEEE
(2017).
2. Weaver, S., Hershberg, B., and Moon, U.K. Digitally
synthesized stochastic 
ash ADC using only standard
digital cells", IEEE Transactions on Circuits and
Systems I: Regular Papers, 61(14), pp. 84{91 (2014).
3. Azin, M. and Bakhtiar, M.S. An 8 bit currentmode
folding ADC with optimized active averaging
network", Scientia Iranica, 15(2), pp. 151{159 (2008).
4. Wul , C. and Ytterdal, T. A compiled 9 bit 20 MS/s
3.5 fJ/conv.step SAR ADC in 28 nm FDSOI for
bluetooth low energy receivers", IEEE Journal of
Solid-State Circuits, 52(2), pp. 1915{1926 (2017).
5. Tao, S. and Rusu, A. A power-ecient continuoustime
incremental sigma-delta ADC for neural recording
systems", IEEE Transactions on Circuits and Systems
I: Regular Papers, 62(6), pp. 1489{1498 (2015).
6. Khateb, F., Khatib, N., Koton, J., et al. Quadrature
oscillator based on novel low-voltage ultra-low-power
quasi-
oating-gate DVCC", Scientia Iranica, 25(6),
pp. 3477{3489 (2018).
7. Huynh, V.T.D., Noels, N., and Steendam, H. E ect
of o set mismatch in time-interleaved ADC circuits
on OFDM-BER performance", IEEE Transactions on
Circuits and Systems I: Regular Papers, 64(8), pp.
2195{2206 (2017).
8. Cho, J.K. A 2.24 mW, 61.8 dB SNDR, 20 MS/s
pipelined ADC with charge-pump-based dynamic biasing
for power reduction in op-amp sharing", IEEE
Transactions on Circuits and Systems I: Regular Papers,
64(6), pp. 1368{1379 (2017).
9. Zahrai, S.A., Zlochisti, M., Dortz, N.L., et al. A lowpower
high-speed hybrid ADC with merged sampleand-
hold and DAC functions for ecient subranging
time-interleaved operation", IEEE Transactions on
Very Large Scale Integration (VLSI) Systems, 25(11),
pp. 3192{3206 (2017).
10. Zhang, M., Noh, K., Fan, X., et al. A 0.8{1.2 V
1050 MS/s 13 bit subranging pipelined-SAR ADC
using a temperature-insensitive time-based ampli er",
IEEE Journal of Solid-State Circuits, 52(11), pp.
2991{3005 (2017).
3478 F. Begum et al./Scientia Iranica, Transactions D: Computer Science & ... 28 (2021) 3464{3479
11. Wu, T.F. and Chen, M.S.W. A subranging-based
nonuniform sampling ADC with sampling event  ltering",
IEEE Solid State-Circuits Letters, 1(4), pp. 78{
81 (2018).
12. Chu, M., Kim, B., and Lee, B.G. A 10 bit 200 MS/s
zero-crossing-based pipeline ADC in 0.13 m CMOS
technology", IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, 23(11), pp. 2671{2675
(2015).
13. Ohhata, K. High-speed, low-power subranging
ADCs", In 2015 International Symposium on Radio-
Frequency Integration Technology (RFIT), pp. 172{
174, IEEE (2015).
14. Hu, Y.S., Shih, C.H., Tai, H.Y., et al. A 0.6 V
6.4 fJ/conversion-step 10 bit 150 MS/s subranging
SAR ADC in 40nm CMOS", In 2014 Asian Solid-State
Circuits Conference, pp. 81{84, IEEE (2014).
15. Chang, H.Y. and Yang, C.Y. A reference voltage
interpolation-based calibration method for 
ash
ADCs", IEEE Transactions on Very Large Scale Integration
(VLSI) Systems, 24(5), pp. 1728{1738 (2016).
16. Pernillo, J. and Flynn, M.P. A 1.5 GS/s 
ash ADC
with 57.7 dB SFDR and 6.4 bit ENOB in 90 nm digital
CMOS", IEEE Transactions on Circuits and Systems
II: Express Briefs, 58(12), pp. 837{841 (2011).
17. Deguchi, K., Suwa, N., Lto, M., et al. A 6 bit 3.5 GS/s
0.9 V 98 mW 
ash ADC in 90 nm CMOS", IEEE
Journal of Solid-State Circuits, 43(10), pp. 2303{2309
(2008).
18. Ismail, A. and Elmasry, M. A 6 bit 1.6 GS/s lowpower
wideband 
ash ADC converter in 0.13 m
CMOS technology", IEEE Journal of Solid-State Circuits,
43(8), pp. 1982{1990 (2011).
19. Yu, H. and Chang, M.C.F. A 1 V 1.25 GS/S 8 bit self
calibrated 
ash ADC in 90 nm digital CMOS", IEEE
Transactions on Circuits and Systems II: Express
Briefs, 55(7), pp. 668{672 (2008).
20. Ku, I.N., Kuan, Y.C., Wang, Y.H., et al. A 40 mW
7 bit 2.2 GS/s time-interleaved subranging CMOS
ADC for low-power gigabit wireless communications",
IEEE Journal of Solid-State Circuits, 47(8), pp. 1854{
1865 (2012).
21. Figueiredo, P.M., Cordoso, P., Lopes, A., et al. A
90 nm CMOS 1.2 V 6b 1 GS/s two-step subranging
ADC", In ISSCC Dig. Tech. papers, pp. 2320{2329,
IEEE (2006).
22. Chung, Y.H. and Wu, J.T. A CMOS 6 mW 10 bit
100 MS/s two-step ADC", IEEE Journal of Solid-State
Circuits, 45(11), pp. 2217{2226 (2010).
23. Chung, Y.H. and Wu, J.T. A 16 mW 8 bit 1 GS/s
digital-subranging ADC in 55 nm CMOS", IEEE
Transactions on Very Large Scale Systems, 23(3), pp.
557{566 (2015).
24. Vander, G. and Verbruggen, B. A 150 MS/s 133 W
7 bit ADC in 90 nm digital CMOS", IEEE Journal of
Solid-State Circuits, 43(12), pp. 2631{2640 (2008).
25. Yoshioka, K., Saito, R., Danjo, T., et al. Dynamic
architecture and frequency scaling in 0.8{1.2 GS/s
7 b subranging ADC", IEEE Journal of Solid-State
Circuits, 50(4), pp. 932{945 (2015).
26. Kobayashi, T., Nogami, K., Shirotori, T., et al. A
current controlled latch sense ampli er and a static
power saving input bu er for low-power architecture",
IEEE Journal of Solid-State Circuits, 28(4), pp. 523{
527 (1993).
27. Upadhyay, P., Kar, R., Mandal, D., et al. Read
stability and power analysis of a proposed novel 8
transistor static random access memory cell in 45 nm
technology", Scientia Iranica, 21(3), pp. 953{962
(2014).
28. Wicht, B., Nirschl, T., and Schmitt-Landsiedel, D.
Yield and speed optimization of a latch type voltage
sense ampli er", IEEE Journal of Solid-State Circuits,
39(7), pp. 1148{1158 (2004).
29. Han, J., Zhang, X., Li, Y., et al. A 64  32 bit 4-
read 2-write low power and area ecient register  le
in 65 nm CMOS", IEICE Electronics Express, 9(16),
pp. 1355{1361 (2012).
30. Schienkel, D., Mensink, E., Kiumperink, E., et al.
A double tail latch type voltage sense ampli er with
18 ps set up+hold time", In International Solid State
Conference, pp. 314{315, IEEE (2007).
31. Jeon, H. and Kim, Y.B. A novel low power, low o set
and high speed CMOS dynamic latched comparator",
Analog Integrated Circuits and Signal Processing,
70(3), pp. 337{336 (2012).
32. Babayan-Mashhadi, S. and Lot , R. Analysis and
design of a low voltage low power double tail comparator",
IEEE Transactions on Very Large Scale Integration
(VLSI) Systems, 22(2), pp. 343{352 (2014).
33. Nakajima, Y., Kato, N., Sakaguchi, A., et al. A 7'bit
1.4 GS/s ADC with o set drift suppression techniques
for one-time calibration", IEEE Transactions on Circuits
and Systems I: Regular Papers, 60(8), pp. 1979{
1990 (2013).
34. Li, W., Li, F., Liu, J., et al. A 13 bit 160 MS/s
pipelined subranging-SAR ADC with low-o set dynamic
comparator", In 2017 Asian Solid-State Circuits
Conference, pp. 6{8, IEEE (2017).
35. Muroya, K., Haiyakawa, D., Sewaki, K., et al.
900 MHz, 3.5 mW, 8 bit pipelined subranging ADC
combining 
ash ADC and TDC", In 2017 International
Symposium on Radio-Frequency Integration Technology
(RFIT), pp. 7{9, IEEE (2017).
36. Chung, Y.H., Hsu, Y.M., Yen, C.W., et al. A 12-bit
160-MS/s ping-pong subranged-SAR ADC in 65 nm
CMOS", In 2017 International SoC Design Conference
(ISOCC), pp. 5{6, IEEE (2017).
37. Ohhata, K. A 2.3-mW, 950-MHz, 8-bit fully-timebased
subranging ADC using highly-linear dynamic
VTC", In 2018 Symposium on VLSI Circuits, pp. 95{
96, IEEE (2018).