Sharif University of Technology Scientia Iranica 1026-3098 21 3 2014 06 01 High Speed Multiplier using High Accuracy Floating Point Logarithmic Number System High Speed Multiplier using High Accuracy Floating Point Logarithmic Number System 826 841 3522 EN Prabir Saha Department of Electronics and Communication Engineering, National Institute of Technology Meghalaya, Shillong, Meghalaya-793003, India Arindam Banerjee Department of Electronics and Communication Engineering, JIS College of Engineering. Kalyani, West Bengal-741235, India Anup Dandapat Department of Electronics and Communication Engineering, National Institute of Technology Meghalaya, Shillong, Meghalaya-793003, India Partha Bhattacharyya Department of Electronics and Telecommunication Engineering, Bengal Engineering and Science University, Shibpur, Howrah-711103, India Journal Article 2013 10 15 The ASIC implementation of the high speed multiplier using high accuracy floating point logarithmic number system is reported in this paper. Most popularly used techniques to compute logarithmic calculations for digital signal processors are lookup table based implementation, polynomial approximation, and Taylor series expansion. But, all of these techniques suffer from low accuracy due to choice of only lower order terms of the expanded series. In the present work, logarithmic conversion is implemented by floating point (IEEE-754 single precision) converting methodology thereby eliminate series expansion which eventually resulted in high accuracy. The improvement in speed, by avoidance of carry propagation, was achieved through canonical signed digit code (CSDC) implementation, while the high accuracy was achieved through an error minimization circuitry specially designed for this purpose. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using 90nm CMOS technology. The propagation delay & power consumption of the resulting (128×128) bit multiplier (divider) was only ~93ns & ~80mW respectively for a layout area of ~25mm2. The implementation offered significant improvement in terms of accuracy, delay and power from earlier reported ones. https://scientiairanica.sharif.edu/article_3522_3cd42ff136a4b9bcd609df333cac4e2e.pdf