Sharif University of Technology Scientia Iranica 1026-3098 15 2 2008 04 01 A Programmable GPS Receiver with Test Circuits in 0.18 m CMOS 2967 EN M. Jenabi Department of Engineering,Auburn University A. Fotowat Ahmady Department of Engineering,Auburn University N. Riahi Department of Engineering,Alzahra University Journal Article 2009 05 30 A 0.18 m single chip GPS receiver, with 19.5 mA current consumption, is implemented in 6.5 mm2. Low-IF architecture was used for a high level of integration and low power consumption. A serial input digital control, with additional testing structure, not adding more than 4% to the Si area, is used in the actual RF circuits, in case of problems, minimizing the number of Si runs. https://scientiairanica.sharif.edu/article_2967_41f9d154e31c6e4889b12b743227bf28.pdf