<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE ArticleSet PUBLIC "-//NLM//DTD PubMed 2.7//EN" "https://dtd.nlm.nih.gov/ncbi/pubmed/in/PubMed.dtd">
<ArticleSet>
<Article>
<Journal>
				<PublisherName>Sharif University of Technology</PublisherName>
				<JournalTitle>Scientia Iranica</JournalTitle>
				<Issn>1026-3098</Issn>
				<Volume></Volume>
				<Issue>Articles in Press</Issue>
				<PubDate PubStatus="epublish">
					<Year>2025</Year>
					<Month>09</Month>
					<Day>23</Day>
				</PubDate>
			</Journal>
<ArticleTitle>Negative Capacitance Gate-Stack Structure with HfO2 Ferroelectric Layer for Improving Digital Performance of the Field Effect Diodes</ArticleTitle>
<VernacularTitle></VernacularTitle>
			<FirstPage></FirstPage>
			<LastPage></LastPage>
			<ELocationID EIdType="pii">23972</ELocationID>
			
<ELocationID EIdType="doi">10.24200/sci.2025.65504.9524</ELocationID>
			
			<Language>EN</Language>
<AuthorList>
<Author>
					<FirstName>Mahziar</FirstName>
					<LastName>Jajipour</LastName>
<Affiliation>Department of Electrical Engineering, Faculty of Engineering, Shahrekord University, Shahrekord 88186, Iran</Affiliation>

</Author>
<Author>
					<FirstName>Seyed Amir</FirstName>
					<LastName>Hashemi</LastName>
<Affiliation>Department of Electrical Engineering, Faculty of Engineering, Shahrekord University, Shahrekord 88186, Iran</Affiliation>
<Identifier Source="ORCID">0000-0002-1825-3706</Identifier>

</Author>
</AuthorList>
				<PublicationType>Journal Article</PublicationType>
			<History>
				<PubDate PubStatus="received">
					<Year>2024</Year>
					<Month>10</Month>
					<Day>15</Day>
				</PubDate>
			</History>
		<Abstract>In this paper, a negative capacitance gate-stack field effect diode (FED) with reduced subthreshold slope, increased on-state current (I&lt;sub&gt;ON&lt;/sub&gt;) and decreased off-state current (I&lt;sub&gt;OFF&lt;/sub&gt;) has been proposed. By using the HfO&lt;sub&gt;2&lt;/sub&gt; ferroelectric layer following by the SiO&lt;sub&gt;2&lt;/sub&gt; dielectric layer under the two gates of the device, a negative capacitance structure is created in the gate-stack. Therefore, the gate control over the channel is strengthened which improves the short channel effects and digital performance of the proposed device. Comparing to the conventional FED, the negative capacitance structure in the gate-stack of the proposed FED amplifies the voltage amplification in the channel which causes larger induced carrier concentration for the same applied gate voltages. As the result, smaller I&lt;sub&gt;OFF&lt;/sub&gt;, higher I&lt;sub&gt;ON&lt;/sub&gt;, higher I&lt;sub&gt;ON&lt;/sub&gt;/I&lt;sub&gt;OFF&lt;/sub&gt; ratio and smaller subthreshold slope are achieved in the proposed FED. In addition, the proposed device exhibits smaller gate capacitance, smaller gate delay time and smaller energy delay product which provide better switching performance with less energy consumption. </Abstract>
		<ObjectList>
			<Object Type="keyword">
			<Param Name="value">Ferroelectric</Param>
			</Object>
			<Object Type="keyword">
			<Param Name="value">Field effect diode</Param>
			</Object>
			<Object Type="keyword">
			<Param Name="value">Negative capacitance</Param>
			</Object>
			<Object Type="keyword">
			<Param Name="value">Subthreshold slope</Param>
			</Object>
		</ObjectList>
<ArchiveCopySource DocType="pdf">https://scientiairanica.sharif.edu/article_23972_e5a7acc236abc42d5e11afede4915282.pdf</ArchiveCopySource>
</Article>
</ArticleSet>
